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Thermal Reliability for FinFET based Designs

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Ansys
Ansys

Thermal reliability faces critical challenges from emerging FinFET-based designs. As designs transition from planar MOS to FinFET transistors, current density increases by 25% and that combined with lower thermal conductivity substrate and 3-D narrow fin structure, local heat gets trapped resulting in thermal-aware EM issues. This presentation introduces Sentinel-TI™, a thermal integrity platform and demonstrates how Chip Thermal Model (CTM™) based power-thermal convergence and interconnect-driven methodology help address the thermal reliability challenges associated with these design. Learn more on our website: https://bit.ly/1sh7I8p, https://bit.ly/1CW3FRT, https://bit.ly/1qk5Juj and (https://bit.ly/1rtrGat)

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6/23/2014 © 2014 ANSYS, Inc. 1 Thermal Reliability for FinFET and 3D-IC Designs Design Automation Conference 2014
6/23/2014 © 2014 ANSYS, Inc. 2 Technology Trends and Thermal Challenges 65nm 40nm 28nm 20nm 16nm Higher Integration on 3D-IC Thermal Interaction on Chips Increasing Gate Density Elevated Thermal Impact Higher Drive Strength Devices Higher EM(T) Impact Shift from Planar to FinFET
6/23/2014 © 2014 ANSYS, Inc. 3 Thermal Reliability • EM (Electromigration) is the gradual displacement of metal atoms due to high current density – Causing open/short circuits • High temperature (T) accelerates EM, a thermal reliability issue – Limiting allowable current density • On-chip Tmax control and thermal run-away avoidance Open Short
6/23/2014 © 2014 ANSYS, Inc. 4 Impact of Self-heating on FinFET • Higher temperature on FinFET expected – For smaller Lg or higher Fin height, Max. Temp increased – 3D narrower fin structure and lower thermal conductivity in substrate causing heat trap • 25ºC increase on FinFET degrades expected lifetime by 3x to 5x on device and metal layers • How to estimate temperature rises? – FEOL (devices), BEOL (wires), and their thermal couplings SHRIVASTAVA et al.: INSIGHT TOWARD HEAT TRANSPORT AND MODELING FRAMEWORK, IEEE TRANSACTIONS ON ELECTRON DEVICES, 2012
6/23/2014 © 2014 ANSYS, Inc. 5 Thermal Coupling Due to Self-Heating FinFET devices with self-heating BEOL wire self-heating couplings Function of Width, Irms, Layer FinFET Function of Rth, finger number, fin number, Power
6/23/2014 © 2014 ANSYS, Inc. 6 Thermal Coupling Effects in BEOL Thermal coupling between wires T Distance from heat source
6/23/2014 © 2014 ANSYS, Inc. 7 RedHawk Totem Self-heat Flow in RedHawk/Totem Tech file / LIB / Dev Models LEF/DEF/GDS DSPF w/ Signal RC Foundry SH Input CTM P/G wire Iavg info Signal wire Irms info Self-heat calculation including thermal coupling Inst Self-heat Report Wire Self-heat Report Thermal Profile / Back-annotation Power EM Run Signal EM Run
6/23/2014 © 2014 ANSYS, Inc. 8 Example Metal Layer Temperature and EM Maps M2 Temp Map Signal EM (M2) Map
6/23/2014 © 2014 ANSYS, Inc. 9 Chip Thermal Interaction on 3D-IC Courtesy of Renesas in 3D-ASIP, 2013 FEM analysis results (Temperature contours) Image Sensor thermal analysis Lid, die, wires, metals, solders modeled in Sentinel-TI
6/23/2014 © 2014 ANSYS, Inc. 10 Temperature Maps Power Maps Thermal BC Chip Thermal CTM Models Chip-Package-System Thermal Solution IC Simulation for Thermal-aware EM (RedHawk/Totem) 3D-IC Chip/Pkg Simulation (Sentinel-TI) System Simulation (Icepak) Chip-aware System Thermal Analysis System-aware Chip Thermal EM Analysis
6/23/2014 © 2014 ANSYS, Inc. 11 RedHawk / Totem Sentinel-TI On-chip Thermal-Aware EM Flow Back-annotation   kT E n a MTTF A J e   Black’s equation for mean-time-to-failure (MTTF) Temp increase causes EM limit decrease Power Library Temperature EM Violations With Temperature Effect Chip Thermal Profile EM Violations Uniform Temperature IC Design Package Design CTM Generation 3D-IC/SoC Thermal Analysis CTM Model
6/23/2014 © 2014 ANSYS, Inc. 12 Transient Thermal Responses Due to High/Low Power Mode Switching Chip Power Map Chip T Map Power Mode Sequence in Time time Lo Lo Lo Hi Hi 푇 푥, 푦, 푧, 푡 = 0 푡 푇푠(푥, 푦, 푧, 푡 − 휏) 휕푃(휏) 휕휏 푑휏 T : Temperature results Ts : Temperature response for power on, a step change P : Power (map) on chips • Optimize thermal sensor placement • Accurate Tmax determination
6/23/2014 © 2014 ANSYS, Inc. 13 Thermal Integrity Coverage • Thermal-aware EM flow needed for tight EM margin on advanced technologies • Thermal related reliability check is a must On-chip thermal-aware EM • Measurement-based FEOL/BEOL Delta-T formula for device/wire self-heat • Simulation-based thermal coupling between wires On-chip FinFET Delta-T • CTM-based thermal analysis on chip-package-system • Good silicon correlation SoC / 3D-IC Tmax Thermal-aware EM EM w/o Thermal
6/23/2014 © 2014 ANSYS, Inc. 14 Summary • FinFET thermal reliability analysis requires accurate and fast thermal simulations • FinFETs require BEOL and FEOL thermal coupling modeling for accuracy • Chip-aware thermal analysis required for accurate package/system analysis • System-aware thermal analysis required for accurate on-die temperatures • Thermal-aware EM is mandatory for FinFET class designs

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Thermal Reliability for FinFET based Designs

  • 1. 6/23/2014 © 2014 ANSYS, Inc. 1 Thermal Reliability for FinFET and 3D-IC Designs Design Automation Conference 2014
  • 2. 6/23/2014 © 2014 ANSYS, Inc. 2 Technology Trends and Thermal Challenges 65nm 40nm 28nm 20nm 16nm Higher Integration on 3D-IC Thermal Interaction on Chips Increasing Gate Density Elevated Thermal Impact Higher Drive Strength Devices Higher EM(T) Impact Shift from Planar to FinFET
  • 3. 6/23/2014 © 2014 ANSYS, Inc. 3 Thermal Reliability • EM (Electromigration) is the gradual displacement of metal atoms due to high current density – Causing open/short circuits • High temperature (T) accelerates EM, a thermal reliability issue – Limiting allowable current density • On-chip Tmax control and thermal run-away avoidance Open Short
  • 4. 6/23/2014 © 2014 ANSYS, Inc. 4 Impact of Self-heating on FinFET • Higher temperature on FinFET expected – For smaller Lg or higher Fin height, Max. Temp increased – 3D narrower fin structure and lower thermal conductivity in substrate causing heat trap • 25ºC increase on FinFET degrades expected lifetime by 3x to 5x on device and metal layers • How to estimate temperature rises? – FEOL (devices), BEOL (wires), and their thermal couplings SHRIVASTAVA et al.: INSIGHT TOWARD HEAT TRANSPORT AND MODELING FRAMEWORK, IEEE TRANSACTIONS ON ELECTRON DEVICES, 2012
  • 5. 6/23/2014 © 2014 ANSYS, Inc. 5 Thermal Coupling Due to Self-Heating FinFET devices with self-heating BEOL wire self-heating couplings Function of Width, Irms, Layer FinFET Function of Rth, finger number, fin number, Power
  • 6. 6/23/2014 © 2014 ANSYS, Inc. 6 Thermal Coupling Effects in BEOL Thermal coupling between wires T Distance from heat source
  • 7. 6/23/2014 © 2014 ANSYS, Inc. 7 RedHawk Totem Self-heat Flow in RedHawk/Totem Tech file / LIB / Dev Models LEF/DEF/GDS DSPF w/ Signal RC Foundry SH Input CTM P/G wire Iavg info Signal wire Irms info Self-heat calculation including thermal coupling Inst Self-heat Report Wire Self-heat Report Thermal Profile / Back-annotation Power EM Run Signal EM Run
  • 8. 6/23/2014 © 2014 ANSYS, Inc. 8 Example Metal Layer Temperature and EM Maps M2 Temp Map Signal EM (M2) Map
  • 9. 6/23/2014 © 2014 ANSYS, Inc. 9 Chip Thermal Interaction on 3D-IC Courtesy of Renesas in 3D-ASIP, 2013 FEM analysis results (Temperature contours) Image Sensor thermal analysis Lid, die, wires, metals, solders modeled in Sentinel-TI
  • 10. 6/23/2014 © 2014 ANSYS, Inc. 10 Temperature Maps Power Maps Thermal BC Chip Thermal CTM Models Chip-Package-System Thermal Solution IC Simulation for Thermal-aware EM (RedHawk/Totem) 3D-IC Chip/Pkg Simulation (Sentinel-TI) System Simulation (Icepak) Chip-aware System Thermal Analysis System-aware Chip Thermal EM Analysis
  • 11. 6/23/2014 © 2014 ANSYS, Inc. 11 RedHawk / Totem Sentinel-TI On-chip Thermal-Aware EM Flow Back-annotation   kT E n a MTTF A J e   Black’s equation for mean-time-to-failure (MTTF) Temp increase causes EM limit decrease Power Library Temperature EM Violations With Temperature Effect Chip Thermal Profile EM Violations Uniform Temperature IC Design Package Design CTM Generation 3D-IC/SoC Thermal Analysis CTM Model
  • 12. 6/23/2014 © 2014 ANSYS, Inc. 12 Transient Thermal Responses Due to High/Low Power Mode Switching Chip Power Map Chip T Map Power Mode Sequence in Time time Lo Lo Lo Hi Hi 푇 푥, 푦, 푧, 푡 = 0 푡 푇푠(푥, 푦, 푧, 푡 − 휏) 휕푃(휏) 휕휏 푑휏 T : Temperature results Ts : Temperature response for power on, a step change P : Power (map) on chips • Optimize thermal sensor placement • Accurate Tmax determination
  • 13. 6/23/2014 © 2014 ANSYS, Inc. 13 Thermal Integrity Coverage • Thermal-aware EM flow needed for tight EM margin on advanced technologies • Thermal related reliability check is a must On-chip thermal-aware EM • Measurement-based FEOL/BEOL Delta-T formula for device/wire self-heat • Simulation-based thermal coupling between wires On-chip FinFET Delta-T • CTM-based thermal analysis on chip-package-system • Good silicon correlation SoC / 3D-IC Tmax Thermal-aware EM EM w/o Thermal
  • 14. 6/23/2014 © 2014 ANSYS, Inc. 14 Summary • FinFET thermal reliability analysis requires accurate and fast thermal simulations • FinFETs require BEOL and FEOL thermal coupling modeling for accuracy • Chip-aware thermal analysis required for accurate package/system analysis • System-aware thermal analysis required for accurate on-die temperatures • Thermal-aware EM is mandatory for FinFET class designs